Computer Architecture
What is a T flip-flop, and how do you make one?
A T flip-flop, or toggle flip-flop, has one data input, T. On each clock edge, if T is 1, its output Q flips to the opposite value; if T is 0, Q holds. Most logic families don't sell one as a part, so it's built from a D flip-flop: wire Q̄ back to D and it toggles on every edge, or add an XOR to get the T input.
How it behaves
| T | Q before the edge | Q after the edge |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Build one from a D flip-flop
A D flip-flop copies D to Q on each rising edge. So whatever you feed D is the next Q:
- Always toggle: wire Q̄, the opposite of Q, to D. Each edge copies the opposite: 0, 1, 0, 1.
- With a T input: put an XOR in front, D = T XOR Q. With T at 0 it feeds Q back and holds; with T at 1 it feeds Q̄ and toggles.
A JK flip-flop with J and K tied together does the same job.
Divide by two
A toggling flip-flop goes high on one rising edge and low on the next, so its output completes one cycle for every two clock cycles: half the frequency. Feed it 1 MHz and you get a 500 kHz square wave, with a clean 50 % duty cycle even if the clock's isn't.
Live experiment
Tick a chain of toggles
Each stage is a flip-flop with Q̄ fed back to D, so it flips on every rising edge of its clock. The first stage is clocked by the button, each later one by the stage before's Q̄. Tick to 3, then once more and watch the bits fall one after another to 0. With four stages it counts to 15.
“Count the clock” is lesson 5 of 6 in Register Reef, Computer Architecture World 1. Free with an account. Lessons unlock in order, so you’ll do the 4 before it first.
Chain them and they count
Clock each toggling stage from the previous stage's Q̄. Q̄ rises at the moment the previous bit falls from 1 to 0, which is exactly when a binary count carries. Two stages count 0, 1, 2, 3, then wrap to 0; four count to 15. A quartz watch runs its crystal at 32,768 Hz because fifteen halvings bring it to exactly 1 Hz.
That's a ripple counter: each stage flips a moment after the one before, so going from 3 to 0 the display reads 2 for an instant. Synchronous counters use T flip-flops too, but clock them all together and set each stage's T to the AND of every bit below it, so a bit flips only when all the lower bits are 1.
Free lesson
Now build it yourself
Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.
“Count the clock” is lesson 5 of 6 in Register Reef, Computer Architecture World 1. Free with an account. Lessons unlock in order, so you’ll do the 4 before it first.
Or start from the very first lesson, no account neededPractice questions
Three quick questions from the lessons. Pick an answer to check it.
Show the answer
Answer: Takes 0: it toggles. Q̄ is the opposite of Q. With Q at 1, Q̄ is 0, and that's what D takes on the tick. Every tick, the opposite.
- Why not “Takes 1”? With Q at 1, Q̄ is 0, and D copies Q̄, so it takes 0, not 1.
- Why not “Stops”? Nothing stops it. With Q̄ wired back to D, every tick takes the opposite.
- Why not “Stays 1”? D is Q̄, the opposite of Q. With Q at 1, D is 0, so the tick changes it.
Show the answer
Answer: The 1s bit goes from 1 to 0, which makes Q̄ rise. A flip-flop acts on a rising edge of its clock. Q̄ rises when Q falls: 1 to 0, the moment the 1s column wraps and carries.
- Why not “Every tick”? Only the 1s stage hears the clock. The 2s stage is clocked by the 1s stage's Q̄, which rises every other tick.
- Why not “Never”? Q̄ of the 1s bit rises every second tick, so the 2s bit flips every second tick.
- Why not “The 1s bit goes from 0 to 1”? When Q rises, Q̄ falls, and a falling edge doesn't clock it. Clocking from Q would flip it here, and count down.
Show the answer
Answer: Halves the frequency of the one before. A toggle flips once every two ticks of its clock.
- Why not “Stays the same”? It flips only on rising edges, so a full cycle of its output takes two clock cycles: half the frequency.
- Why not “Doubles it”? A toggling stage flips once per clock cycle, so a full cycle of its own output takes two clock cycles. It runs slower, not faster.
- Why not “Adds one”? The whole chain adds one per tick. Each stage on its own halves the frequency.
“Count the clock” is lesson 5 of 6 in Register Reef, Computer Architecture World 1. Free with an account. Lessons unlock in order, so you’ll do the 4 before it first.
Questions people ask
What is the characteristic equation of a T flip-flop?
Q(next) = T XOR Q. With T at 0 the XOR passes Q through unchanged, so it holds; with T at 1 it inverts Q, so it toggles. That one equation is the whole behaviour, applied at each clock edge.
How is a T flip-flop related to a JK flip-flop?
Tie a JK flip-flop's J and K inputs together and call them T. With both at 0 a JK holds, and with both at 1 it toggles, which is exactly a T flip-flop.
Why does a T flip-flop divide the clock by two?
With T held at 1 it flips once on every rising edge, so its output goes high on one edge and low on the next. One full output cycle takes two clock cycles: half the frequency, and an even 50 % duty cycle whatever the clock's own duty.
Related topics
- How a D flip-flop worksCopy D to Q at the clock's rising edge, then hold it: one bit of memory.
- How a binary counter divides a clock by 2, 4, 8 and 16Flip-flops that toggle, chained: each one halves the clock, together they count.
- Synchronous vs asynchronous countersBits that wait for each other, or bits that change on the same tick.
- How a register holds a value until it's told to loadA flip-flop with a picker in front: load when told, keep what you have the rest of the time.