Digital Logic
How a binary counter divides a clock by 2, 4, 8 and 16
A binary counter is a chain of flip-flops, each wired to toggle, flip its output, on every tick it receives. Each stage flips once for every two ticks of the stage before, so it runs at half the frequency. Read the outputs together and they count in binary; take just the last one and you have a frequency divider.
One flip-flop halves a clock
Feed a D flip-flop's inverted output, Q̄, back into its D. On each rising clock edge it copies the opposite of what it holds, so Q flips: 0, 1, 0, 1, one change per tick. A full cycle of Q, high then low, takes two clock cycles:
A toggling flip-flop clocked at 8 Hz blinks at 4 Hz, whatever shape the clock's pulses are, because it only acts on rising edges.
Chain them and they count
Clock the second stage from the first, the third from the second, and so on. Each one halves again, so n stages divide by 2ⁿ: four stages turn 2 Hz into 1, 0.5, 0.25 and 0.125 Hz.
Live experiment
A clock halved again and again
A 2 Hz clock ticks into a chain of four toggling flip-flops. Each light blinks at half the rate of the one before, from 1 Hz down to 0.125 Hz, and the display reads the four lights as a binary number. Run the clock, or tick it by hand.
“Clocks and counters” is lesson 6 of 6 in Logic Grid, Electronics World 7. Free with an account. Lessons unlock in order, so you’ll do the 47 before it first.
Now read the four outputs as one number, the first stage as the 1s bit and the last as the 8s. With rising-edge flip-flops, each stage is clocked from the Q̄ of the stage before. Q̄ rises when Q falls from 1 to 0, which is exactly when that column wraps round and carries, so the next bit flips. The display counts 0, 1, 2 … 15, then rolls over to 0, like an odometer going from 9999 to 0000.
Clock each stage from Q instead, and the chain counts down.
Ripple, and its catch
This chain is a ripple counter: each stage waits for the one before to change, so a change ripples down the line one flip-flop delay at a time. Going from 7 (0111) to 8 (1000), the bits flip one after another and for a few nanoseconds the outputs show 6, 4 and 0 on the way. For a blinking light that's harmless. For logic that reads the count on every clock edge it isn't, which is why processors use synchronous counters, where every bit changes on the same edge. Microcontroller timers, the ones behind millis() and PWM, are counters like this, clocked from the chip's own oscillator.
Free lesson
Now build it yourself
Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.
“Clocks and counters” is lesson 6 of 6 in Logic Grid, Electronics World 7. Free with an account. Lessons unlock in order, so you’ll do the 47 before it first.
Or start from the very first lesson, no account neededPractice questions
Three quick questions from the lessons. Pick an answer to check it.
Show the answer
Answer: rolls round to zero. Every stage is at 1, so every stage flips back to 0 at once, like an odometer going from 9999 to 0000. Then it starts climbing again.
- Why not “stops at the top”? A plain counter has nothing that stops it: every stage at 1 flips to 0 on the next tick, so it wraps.
- Why not “counts back down”? Counting down needs different wiring. An up counter at its top value wraps round to zero.
Show the answer
Answer: 4 Hz. Q flips once per tick, so one whole blink, on then off, takes two ticks. 8 ÷ 2 = 4 Hz.
- Why not “2 Hz”? 2 Hz is what a second stage would give, halving again. One toggling flip-flop divides by 2, not 4.
- Why not “8 Hz”? 8 Hz is the clock itself. The flip-flop needs two of its ticks for each full blink, on then off.
- Why not “16 Hz”? 16 Hz would be twice the clock. A flip-flop can only change on its clock's edges, so it can't run faster.
Show the answer
Answer: The 1s bit goes from 1 to 0, which makes Q̄ rise. A flip-flop acts on a rising edge of its clock. Q̄ rises when Q falls: 1 to 0, the moment the 1s column wraps and carries.
- Why not “Every tick”? Only the first stage hears every tick. The 2s bit is clocked by the 1s bit's Q̄, which rises once every two ticks.
- Why not “Never”? It flips every other tick, whenever the 1s bit wraps from 1 to 0 and carries.
- Why not “The 1s bit goes from 0 to 1”? When the 1s bit goes from 0 to 1, Q̄ falls. A falling edge doesn't clock a rising-edge flip-flop.
“Clocks and counters” is lesson 6 of 6 in Logic Grid, Electronics World 7. Free with an account. Lessons unlock in order, so you’ll do the 47 before it first.
Questions people ask
How does a flip-flop divide frequency by 2?
Wired to toggle, a flip-flop flips its output once on each rising edge of its clock. One full cycle of the output, high then low, takes two clock cycles, so the output runs at exactly half the clock's frequency.
How many flip-flops do I need to divide by 1000?
A plain chain only divides by powers of two: 10 stages divide by 1024. For an exact 1000, use a counter that resets itself when it reaches 1000, or chain decade counters that each divide by 10.
Why do watches use a 32,768 Hz crystal?
32,768 is 2 to the power 15, so fifteen halving stages bring it down to exactly 1 Hz, one tick a second. The frequency is also high enough to be above human hearing and low enough to use very little power.
Related topics
- How a D flip-flop worksCopy D to Q at the clock's rising edge, then hold it: one bit of memory.
- Binary numbers explainedPlaces worth 1, 2, 4 and 8: add up the bits that are on, and four wires count to 15.
- Synchronous vs asynchronous countersBits that wait for each other, or bits that change on the same tick.
- How a shift register worksFlip-flops in a chain that pass bits along: serial in, parallel out.