Computer Architecture
Synchronous vs asynchronous counters
In an asynchronous, or ripple, counter, only the first flip-flop gets the clock, and each later stage is clocked by the one before it, so a change ripples down the chain. In a synchronous counter, every flip-flop shares the same clock, and logic gates work out in advance which bits should flip. Ripple counters are simpler; synchronous counters change every bit on the same edge, with no glitches and no waiting.
The ripple counter
Wire each D flip-flop to toggle, Q̄ back to D. The clock drives only the first stage; each next stage is clocked from the previous stage's Q̄, which rises at the moment that bit falls from 1 to 0, a carry. It counts, with almost no extra parts.
The catch is time. Each flip-flop takes a few nanoseconds to respond. Going from 3 (011) to 4 (100), the 1s bit falls first, then the 2s, then the 4s rises, and for those few nanoseconds the outputs show 2 and then 0. A 32-bit ripple counter with 1 ns per stage can take 32 ns to settle, longer than a modern clock tick.
The synchronous counter
Give every flip-flop the same clock. Before each tick, gates work out every bit's next value from the current count. A bit flips when all the bits below it are 1, the moment they all wrap round:
The XOR with Q means flip if the right side is 1, keep if it's 0. The 1s bit flips every tick. The 2s bit flips when the 1s is 1. The 4s bit flips only when the 1s and the 2s are 1, so from 3 (011) every bit flips at once and the count goes to 4 (100) in a single step.
Live experiment
Three bits, one tick
A three-bit synchronous counter. Gates work out every bit's next value before the tick: D0 = NOT Q0, D1 = Q1 XOR Q0, D2 = Q2 XOR (Q1 AND Q0). Tick, and every bit changes at once. Leave the AND out and 2 jumps to 7.
“Count together” is lesson 2 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 8 before it first.
Which to use
| Ripple | Synchronous | |
|---|---|---|
| Clocking | each stage from the last | one clock for all |
| Extra gates | none | grow with the width |
| Settling | one delay per bit | about one delay |
| Glitches | brief wrong counts | none |
Use a ripple counter where only the slowest output matters, like a watch dividing 32,768 Hz down to 1 Hz. Use a synchronous counter wherever other logic reads the count on the next clock edge, which is nearly everywhere inside a processor: the program counter, timers and address generators are all synchronous. Wider synchronous counters speed up the carry with lookahead, just as fast adders do.
Free lesson
Now build it yourself
Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.
“Count together” is lesson 2 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 8 before it first.
Or start from the very first lesson, no account neededPractice questions
Three quick questions from the lessons. Pick an answer to check it.
Show the answer
Answer: Both the 1s and 2s bits are 1. A bit flips when every bit below it is 1, the moment they all wrap. D2 = Q2 XOR (Q1 AND Q0).
- Why not “Every tick”? Flipping on every tick is the 1s bit's rule. The 4s bit flips once every four ticks.
- Why not “Never”? The 4s bit does flip, whenever the count below it wraps from 3 to 0.
- Why not “The 2s bit is 1”? With only the 2s bit at 1, the count is 2 or 6, and adding one doesn't carry into the 4s yet.
Show the answer
Answer: All on the same clock edge. One clock, gates deciding each bit's next value.
- Why not “One after another”? One after another is a ripple counter. A synchronous counter clocks every bit at the same instant.
- Why not “At random”? Nothing is random: gates work out each bit's next value, and the shared clock edge loads them all.
- Why not “Only when reset”? Reset is only one use of the clock. On every tick, reset or not, all the bits change together.
Show the answer
Answer: The 1s bit falls, its Q̄ rises, and that makes the 2s bit fall: 0. Only the 1s stage hears the clock. Its fall from 1 to 0 makes its Q̄ rise, and that rising edge clocks the 2s stage a moment later. Two bits can't hold 4, so it wraps to 0.
- Why not “Both bits flip at exactly the same instant”? In a ripple counter only the 1s stage hears the clock, so the 2s bit changes a moment after the 1s bit, not with it.
- Why not “It shows 4”? Two bits can only hold 0 to 3, so 3 plus one wraps to 0.
- Why not “Only the 1s bit changes: 2”? The 1s bit falling makes its Q̄ rise, which clocks the 2s bit, so the 2s bit flips too.
“Count together” is lesson 2 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 8 before it first.
Questions people ask
What is the difference between synchronous and asynchronous counters?
In an asynchronous or ripple counter, only the first flip-flop gets the clock and each later one is clocked by the stage before, so changes ripple down the line. In a synchronous counter every flip-flop shares one clock and gates decide which bits flip, so they all change at once.
Why are ripple counters slower?
The top bit can't change until every bit below it has changed, one flip-flop delay each. A 32-bit ripple counter with 1 ns per stage needs up to 32 ns to settle, while a synchronous counter settles in about one flip-flop delay plus its gates.
Are ripple counters ever used?
Yes, where only the final count or the slowest output matters, such as dividing a watch crystal down to 1 Hz. They need no extra gates and use very little power. Anything that reads the count on every clock edge uses a synchronous counter.
Related topics
- How a binary counter divides a clock by 2, 4, 8 and 16Flip-flops that toggle, chained: each one halves the clock, together they count.
- How a D flip-flop worksCopy D to Q at the clock's rising edge, then hold it: one bit of memory.
- What does the program counter do in a CPU?The register that says which instruction comes next, and how jumps make loops.
- Half adder vs full adderA half adder adds two bits; a full adder adds the carry too, so they chain.