Why a flip-flop clock divider gives a 50% duty cycle

Wire a D flip-flop's Q̄ back to its own D and it toggles: on every rising clock edge it flips. Its output runs at half the clock's frequency. And because it only changes on rising edges, which come exactly once per clock period, the output is high for one whole period and low for the next. That's a 50% duty cycle, however lopsided the incoming clock is.

Divide by 2

On each rising edge the flip-flop copies D, which is the opposite of Q, so Q goes 0, 1, 0, 1. One full cycle of Q, high then low, takes two clock periods:

An 8 Hz clock gives a 4 Hz output; a 16 MHz one gives 8 MHz.

Why the output is always 50%

Take a clock that's high for only a quarter of each period. The flip-flop doesn't care how long the clock stays high: it ignores the falling edge, and a clock held high isn't an edge at all. Only the rising edges count, and they arrive exactly one period apart. So Q holds each value for exactly one period, and its duty cycle is 50%.

Live experiment

Feed a divider a sloppy clock

A clock drives a chain of one, two or three toggling flip-flops. Make the clock even, or high for only a quarter or four fifths of each tick, and watch the scope: the clock goes lopsided, but every output is on for whole ticks and off for as many, a perfect square wave at half the rate.

Try it yourself: free lesson

“Half the beat” is lesson 1 of 6 in Toggle Tides, Digital Logic World 3. Free with an account. Lessons unlock in order, so you’ll do the 14 before it first.

This is why many oscillators run at twice the frequency they need and divide by 2: a crystal oscillator's output is rarely an exact 50%, and the divided clock always is.

Chains divide by powers of 2

Clock a second toggle from the first one's Q̄ and it halves again; n stages divide by 2ⁿ, and every stage's output is a clean 50% square wave. Read the stages together and the chain is a binary counter.

Other ratios

Toggles divide only by powers of 2. For 3, 5 or 10, count the ticks and start again at 0: a divide-by-10 counts 0 to 9. The output repeats every ten ticks, but it's only 50% if the design arranges it: the CD4017 decade counter's carry output, for one, is high for five counts and low for five. Odd ratios need a trick, such as a second flip-flop on the falling edge, to reach an even 50%.

What a divider can't fix

It fixes the duty cycle, not the timing. Every output edge follows an input rising edge, so if those edges wobble, the output's edges wobble with them. And the input's period must be steady: a divider halves whatever rate it's given.

Microcontroller timers run their clock through a divider called a prescaler, dividing 16 MHz by 8, 64 or 256 before counting, and guitar octave pedals use a toggle to halve a note's pitch.