Computer Architecture
Synchronous vs asynchronous reset in digital logic
A reset puts every flip-flop in a circuit into a known state, usually 0. A synchronous reset does it on the next clock edge, through each flip-flop's D input. An asynchronous reset does it at once, through a separate pin that overrides the clock. Counters, state machines and processors all need one, because flip-flops power up holding whatever they like.
Why a reset at all
At power-on, each flip-flop settles into 0 or 1 more or less at random. A counter might wake at 2, a state machine in a state it should never reach, and a processor's program counter at an address full of nonsense. Holding RESET for a tick puts every register at its starting value, and the same line can restart a loop or a timer later.
Synchronous: one AND per bit
Take a counter's normal next-value logic. Between it and each D input, put an AND gate fed by NOT RESET:
With RESET at 0, NOT RESET is 1, and every next value passes unchanged. With RESET at 1, every D is 0, and the next rising edge loads zeros everywhere at once. One NOT gate feeds all the ANDs, and nothing touches the clock.
Live experiment
Raise RESET, then tick
A two-bit counter with a synchronous reset: NOT RESET ANDed into each bit's next value. Count to 2, raise RESET and watch both D inputs drop to 0 while the display still says 2: the clear lands on the tick. Then give only the 1s bit its AND and see the reset fail.
“Back to zero” is lesson 3 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 9 before it first.
Raise RESET and the D inputs go to 0 straight away, but the outputs keep their old count until the tick. Hold RESET for three ticks and the counter sits at 0; drop it and counting starts again from there. Leave the 2s bit without its AND and it follows its own rule, so a reset from 2 leaves 2.
Asynchronous: clear it now
Many flip-flops have a dedicated clear pin that forces Q to 0 the instant it's asserted, no clock needed. The 74HC74 has one on each of its two flip-flops, and the RESET pin on an Arduino Uno's AVR chip works this way too. It acts even when the clock isn't running yet, which makes it popular at power-up.
The catch is the release. If reset lets go just as a clock edge arrives, some flip-flops leave reset on that edge and some on the next, and a counter or state machine starts out of step with itself. The usual cure is to assert asynchronously and release synchronously: the reset pulls everything to 0 at once, but its release passes through two flip-flops on the system clock first, so every register comes out on the same edge.
Which to use
| Synchronous | Asynchronous | |
|---|---|---|
| Acts | On the next clock edge | Immediately |
| Needs a running clock | Yes | No |
| Timing | Like any other data signal | Release must be synchronised |
| Built from | An AND gate per bit | A clear pin on each flip-flop |
Either way, keep the reset off the clock line itself. Gating a clock with a reset is the classic way to build a flaky circuit.
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Now build it yourself
Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.
“Back to zero” is lesson 3 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 9 before it first.
Or start from the very first lesson, no account neededPractice questions
Three quick questions from the lessons. Pick an answer to check it.
Show the answer
Answer: 2: the 2s bit keeps counting its own way. The 1s bit clears. The 2s bit's next value is still Q1 XOR Q0 = 1 XOR 0 = 1. Every bit needs the AND.
- Why not “0”? The 2s bit has no reset AND, so its next value, Q1 XOR Q0 = 1, still reaches its D. Only the 1s bit clears.
- Why not “3”? 3 needs the 1s bit at 1, but its AND holds it at 0 while RESET is high.
- Why not “1”? That would need the 1s bit set and the 2s bit clear. The AND forces the 1s bit to 0, and the unguarded 2s bit stays 1.
Show the answer
Answer: Between the next-value rule and the D input. It gates what the flip-flop will take on the next tick. The clock stays untouched, like always.
- Why not “On the clock”? Gating the clock delays it and can make false edges. The reset belongs in the data path, just before D.
- Why not “On the display”? Blanking the display hides the count while the flip-flops carry on. The D inputs themselves have to be forced to 0.
- Why not “Between Q and the XOR”? That only changes one input of the 2s bit's XOR. The reset must force every D to 0, so it goes after the rule, right before D.
Show the answer
Answer: NOT RESET is the same signal everywhere; one gate feeds every AND. One output can feed many inputs. One NOT, as many ANDs as there are bits.
- Why not “Each bit needs its own”? Every bit needs the same NOT RESET signal, and one gate's output can feed many inputs.
- Why not “It isn't”? It is: one NOT RESET drives every bit's AND, so a second NOT would only duplicate it.
- Why not “NOT gates are expensive”? Cost isn't the reason. One NOT is enough because its output is the same for every bit.
“Back to zero” is lesson 3 of 6 in Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 9 before it first.
Questions people ask
What is the difference between a synchronous and an asynchronous reset?
A synchronous reset works through each flip-flop's D input, so the registers clear on the next active clock edge. An asynchronous reset uses a separate pin on the flip-flop that forces Q to 0 the moment it's asserted, with or without a clock.
Why does a counter or processor need a reset at all?
Flip-flops power up holding 0 or 1 more or less at random. Without a reset, a counter can start at any value and a processor's program counter can start at an address that holds nonsense. A reset gives every register a known starting value.
What does 'assert asynchronously, release synchronously' mean?
The reset clears everything at once, like an asynchronous reset, but its release is passed through two flip-flops on the system clock first. Every register then leaves reset on the same clock edge, so nothing starts a tick ahead of the rest.
Related topics
- What does the program counter do in a CPU?The register that says which instruction comes next, and how jumps make loops.
- Synchronous vs asynchronous countersBits that wait for each other, or bits that change on the same tick.
- How a D flip-flop worksCopy D to Q at the clock's rising edge, then hold it: one bit of memory.
- The fetch-decode-execute cycle explainedFetch an instruction, decode it, carry it out, repeat: how every CPU runs.