Computer Architecture
How to build a program counter from flip-flops and gates
A program counter holds the address of the next instruction. This guide builds a 2-bit one from two D flip-flops and eleven gates. On each clock tick it counts on by one, jumps to the address on two switches when LOAD is 1, and clears to 0 when RESET is 1. A wider counter repeats the same three stages for every extra bit.
What it has to do
Inputs: the jump target IN1 and IN0, plus LOAD, RESET and the clock. Outputs: Q1 and Q0, shown on a display. On every rising edge:
- RESET is 1: go to 0, whatever else is set
- LOAD is 1: take the switches
- otherwise: count on, and wrap from 3 to 0
Stage 1: the next count
Both flip-flops share one clock, so this is a synchronous counter. The 1s bit flips every tick, so its next value is Q̄0. The 2s bit flips whenever the 1s bit is 1, so its next value is Q0 XOR Q1.
Stage 2: the LOAD picker
In front of each bit, a picker chooses between the switch and the next count:
One NOT gate makes NOT LOAD for both bits. Exactly one of the two ANDs is open at a time, so exactly one value reaches the OR.
Stage 3: the reset
A second shared NOT makes NOT RESET, and one more AND per bit sits last, right before D. Because it comes after the picker, RESET beats LOAD.
Live experiment
Count, jump, reset
The finished program counter, before you build it. Set the jump address on the switches and tick by hand: count, LOAD a jump to 3, watch it wrap, then RESET. Two broken builds, one without the RESET ANDs and one without the LOAD pickers, show which test catches each.
“Project: Program counter” is the project that ends Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 13 before it first.
Parts list
| Part | How many | Job |
|---|---|---|
| D flip-flop | 2 | Hold Q0 and Q1, both on the same clock |
| XOR | 1 | The 2s bit's next count |
| NOT | 2 | NOT LOAD and NOT RESET, shared |
| AND | 6 | Two per picker, one per reset |
| OR | 2 | One per picker |
Build and test in order
- Plain counter. Wire the next-count logic straight to D and tick: 0, 1, 2, 3, 0.
- Add the pickers. Set the switches to 11, LOAD to 1, tick: 3. LOAD back to 0, tick: 0, as it wraps.
- Add the reset ANDs. From any count, RESET to 1 and tick: 0. Drop it and it counts from there.
A full test runs them together: count to 1, jump to 3, count on to 0, two more ticks to 2, reset to 0, then count to 1.
Where it goes next
Put a memory's address lines on Q and its data lines on an instruction decoder, and this counter steps a processor through a program. A jump instruction drives LOAD; the power-on reset drives RESET.
Free lesson
Now build it yourself
Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.
“Project: Program counter” is the project that ends Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 13 before it first.
Or start from the very first lesson, no account neededPractice questions
Three quick questions from the lessons. Pick an answer to check it.
Show the answer
Answer: Goes to 0 and stays there: both gates are closed, so D is 0. Two closed gates give 0 into the OR, so D is 0 for ever. One gate gets LOAD, the other NOT LOAD.
- Why not “Toggles”? Toggling needs Q̄ to reach D. Both AND gates give 0, so D is stuck at 0.
- Why not “Loads”? Loading needs LOAD at 1. Here LOAD is 0, so the gate passing IN is closed too.
- Why not “Counts”? To count, the next-count gate must be open when LOAD is 0, which needs NOT LOAD on it.
Show the answer
Answer: NOT RESET AND the bit's next value. With RESET high, every D is 0.
- Why not “Nothing”? Without a reset path the counter can't be sent back to 0, and it powers up wherever its flip-flops land.
- Why not “RESET XOR next”? An XOR with RESET would invert each next value, scrambling the count instead of clearing it.
- Why not “RESET OR next”? An OR with RESET would force every bit to 1 on reset, not 0.
Show the answer
Answer: 1, 2, 7: the 4s flips as soon as the 2s is 1. Without the AND the 4s bit flips whenever the 2s bit is 1, not only when the 1s is 1 too. The count goes wrong at the third tick.
- Why not “1, 3, 5”? The lower two bits are unchanged, so 1 is still followed by 2. The fault shows after 2, when the 4s bit flips early.
- Why not “1, 2, 3, 4”? That needs the 4s bit to flip only when both lower bits are 1, which is exactly the AND that's missing.
- Why not “0 for ever”? The 1s and 2s bits still count normally, so the display moves on the very first tick.
“Project: Program counter” is the project that ends Fetch Fjord, Computer Architecture World 2. Free with an account. Lessons unlock in order, so you’ll do the 13 before it first.
Questions people ask
How many gates does a 2-bit program counter need?
This design uses 2 D flip-flops and 11 gates: one XOR for the next count, a shared NOT LOAD and NOT RESET, and for each bit two ANDs and an OR for the picker plus one AND for the reset.
What happens if LOAD and RESET are both 1?
Reset wins. The reset AND is the last gate before each D, so NOT RESET at 0 forces every D to 0 whatever the picker chose. Put the picker after the reset instead and a jump could escape the reset.
How do I make the program counter wider?
Repeat the same three stages for each new bit. Bit k flips when every bit below it is 1, so its next value is Qk XOR (Q0 AND Q1 AND … the bits below). Each bit then gets its own picker and reset AND, sharing the one NOT LOAD and NOT RESET.
Related topics
- What does the program counter do in a CPU?The register that says which instruction comes next, and how jumps make loops.
- Synchronous vs asynchronous countersBits that wait for each other, or bits that change on the same tick.
- How a D flip-flop worksCopy D to Q at the clock's rising edge, then hold it: one bit of memory.
- The fetch-decode-execute cycle explainedFetch an instruction, decode it, carry it out, repeat: how every CPU runs.