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Digital Logic

How an SR latch remembers a bit

An SR latch stores one bit using two gates whose outputs feed back into each other's inputs. Pulse S (set) and the output Q goes to 1; pulse R (reset) and it goes to 0; leave both at 0 and it holds whatever it last had. It's the simplest memory there is, and the starting point for every flip-flop and register.

Two NOR gates in a loop

Take two NOR gates. The first takes R and the second gate's output; its output is Q. The second takes S and Q; its output is Q̄, the opposite of Q.

Press S. The second gate sees a 1, so Q̄ goes to 0. The first gate now sees R = 0 and Q̄ = 0, so Q goes to 1. Let go of S: the second gate sees S = 0 and Q = 1, so Q̄ stays 0, and that keeps Q at 1. The two gates hold each other in place. That loop is memory.

SRQ next
00Q (hold)
101 (set)
010 (reset)
11not allowed

At power-up, before S or R has been pulsed, the loop could be holding either value. Simulators show it as X, unknown, and real circuits add a reset so they start from a known state.

The D latch: add a door

An SR latch needs two inputs and has a forbidden combination. A D latch fixes both with two ANDs in front:

S = D · ENABLE, R = NOT D · ENABLE

While ENABLE is 1, the door is open: D = 1 sets the latch and D = 0 resets it, so Q follows D. When ENABLE goes to 0, both ANDs give 0, and the loop holds the last value, whatever D does next. S and R can never both be 1.

Live experiment

A latch with a door

This D latch is a NOR loop with a door in front. With ENABLE at 1, Q copies D; set ENABLE to 0 and the loop holds whatever it had, whatever D does. At power-up it holds nothing yet: X. The strip records D, ENABLE and Q at every flip.

Try it yourself: free lesson

“Latches” is lesson 6 of 6 in Nand Narrows, Digital Logic World 2. Free with an account. Lessons unlock in order, so you’ll do the 12 before it first.

Latch or flip-flop?

A D latch is transparent: for the whole time ENABLE is high, changes on D pass straight through to Q. A D flip-flop looks at D only at the instant its clock rises, which makes timing far easier to reason about in big circuits. Latches still appear where speed or size matters, and an SR latch is the classic way to debounce a two-way switch: the first touch sets or resets it, and the bounces that follow change nothing.

Free lesson

Now build it yourself

Each lesson comes in three short parts: see the idea, try it on a live board, then build it yourself, with quick checks as you go.

Try it yourself: free lesson

“Latches” is lesson 6 of 6 in Nand Narrows, Digital Logic World 2. Free with an account. Lessons unlock in order, so you’ll do the 12 before it first.

Or start from the very first lesson, no account needed

Practice questions

Three quick questions from the lessons. Pick an answer to check it.

  1. Question 1 of 3Release SET after pressing it. Q…
    Show the answer

    Answer: Stays 1: Q̄ is 0 and keeps the Q gate at 1. With SET back at 0 the Q̄ gate sees 0 and Q = 1, so Q̄ stays 0; the Q gate sees RESET 0 and Q̄ 0, so Q stays 1. The loop holds itself.

    • Why not “Flickers”? The loop is stable: each gate's output holds the other gate's input steady, so nothing flickers.
    • Why not “Goes X”? X is the unknown state before anything has been stored. After a SET, the latch knows it holds 1.
    • Why not “Goes 0”? Q only goes to 0 if RESET is pressed. Letting go of SET leaves both inputs at 0, which means hold.
  2. Question 2 of 3Before SET or RESET has ever been pressed, Q is…
    Show the answer

    Answer: Unknown: the loop could hold either value. The loop is happy holding 0 or 1, and nothing has told it which. The simulator shows X. Real circuits add a reset at power-up so they start known.

    • Why not “Always 0”? Nothing forces a 0 at power-up. The loop is just as happy holding 1, and which one it lands on is chance.
    • Why not “Flickering”? The loop settles into one of its two stable states almost at once; it doesn't keep flickering.
    • Why not “Always 1”? Nothing forces a 1 either. Without a reset, the starting value is unknown.
  3. Question 3 of 3Pressing SET and RESET together, then releasing both at once…
    Show the answer

    Answer: Leaves the latch undecided: both gates race to switch. Held together, both outputs are 0. Released together, both gates switch at the same moment and keep fighting. Designs simply never let SET and RESET happen together.

    • Why not “Resets it”? For the same reason it isn't reliably reset: both gates switch together and race.
    • Why not “Does nothing”? Something does happen: while held, both outputs are 0, and on release the two gates fight over the result.
    • Why not “Sets it”? Releasing both at once gives neither input the last word, so the latch isn't reliably set.
Keep practising: free lesson

“Latches” is lesson 6 of 6 in Nand Narrows, Digital Logic World 2. Free with an account. Lessons unlock in order, so you’ll do the 12 before it first.

Questions people ask

What is an SR latch?

The simplest memory circuit: two NOR gates (or two NAND gates), each feeding its output into the other's input. A pulse on S sets the output Q to 1, a pulse on R resets it to 0, and with both inputs at 0 it holds whatever it last had.

Why is S = 1, R = 1 not allowed in an SR latch?

In the NOR version both outputs go to 0, so Q and Q̄ are no longer opposites. Worse, if both inputs then return to 0 together, the two gates race and the latch can land either way. Designs simply never let both happen at once.

What is the difference between a latch and a flip-flop?

A latch is level-sensitive: while its enable is active, its output follows the input. A flip-flop is edge-triggered: it copies its input only at the instant the clock rises, and ignores it the rest of the time.

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